1. Field of the Invention
This invention relates generally to random access memory, and more particularly to transferring data between asynchronous clock domains.
2. Description of the Related Art
Often, computer related devices require communication across differing clock domain boundaries. For example, components related to a system clock may operate in the system clock domain while memory components operate in a different data clock domain. One such memory device is double data rate (DDR) synchronous dynamic random access memory (SDRAM), which utilizes a data strobe signal to transfer data on each rising and falling edge of the data strobe signal. To coordinate the transfer of data to and from a DDR SDRAM memory device, a synchronization circuit in the form of a memory controller often is used with the memory device. The memory controller uses the data strobe signal to determine when the read data is valid and can be latched.
FIG. 1 is a block diagram showing a prior art DDR DIMM 100 architecture using DDR SDRAM integrated circuit devices. As illustrated in FIG. 1, the DDR DIMM 100 includes a plurality of DDR memory devices 102a-102h disposed on a printed circuit board 104. Coupled to each DDR memory device 102a-102h is a set of data/data strobe signal (DQS) lines 106. Each set of data/DQS lines 106 provide I/O for each DDR memory devices 102a-102h. As will be appreciated by those skilled in the art, DDR memory devices require separate control lines that are unique to each memory device and distributed in parallel. These parallel control lines are known as data strobe signal (DQS) lines and are generated from a differential clock fed to each DDR memory device 102a-102h and a DLL located within each DDR memory device 102a-102h. The DQS signal allows each DDR memory device 102a-102h to launch data from the memory device at the same instant as a data-valid signal. Also included in the DDR DIMM 100 are clock and command signal lines 108, which provide clock and command signals to each of the DDR memory devices 102a-102h. 
As illustrated in FIG. 1, the clock and command signal lines 108 are connected to each DDR memory device 102a-102h on the DDR DIMM 100 in a parallel configuration. That is, the clock and command signal lines 108 are provided to each DDR memory device 102a-102h simultaneously. In this manner, each DDR memory device 102a-102h provides or receives data to/from its associated data/DQS lines 106 at approximately the same time. Because each DDR memory device 102a-102h provides or receives data to/from its associated data/DQS lines 106 at approximately the same time, the relationship between the system clock and the data clock is known at the time of design. However, there are instances when this relationship is unknown at the time of design. Such an instance is when double data rate three (DDR3) SDRAM is used, wherein asynchronous clock domains present unknown timing relationships at design.
For example, FIG. 2 is a block diagram showing a prior art DDR3 DIMM 200 architecture using DDR3 SDRAM integrated circuit devices. As illustrated in FIG. 2, the DDR3 DIMM 200 includes a plurality of DDR3 memory devices 202a-202h disposed on a printed circuit board 204. Coupled to each DDR3 memory device 202a-202h is a set of data/DQS lines 206, which provide I/O for each DDR3 memory devices 202a-202h. Also included in the DDR3 DIMM 200 are clock and command signal lines 208, which provide clock and command signals to each of the DDR3 memory devices 202a-202h. 
Unlike the DDR DIMM 100 illustrated in FIG. 1, the DDR3 DIMM 200 is configured in a fly-by topology in which the clock and command signal lines 208 are connected in series to each DDR3 memory device 202a-202h on the DDR3 DIMM 200 in a daisy chain configuration. That is, the clock and command signal lines 208 are first provided to DDR3 memory device 202a, then to DDR3 memory device 202b, then to DDR3 memory device 202c, and so on to DDR3 memory device 202h. Consequently, DDR3 memory device 202a receives and acts on the received clock and command signals prior to DDR3 memory device 202b. Similarly, DDR3 memory device 202b receives and acts on the received clock and command signals prior to DDR3 memory device 202c, and so on until DDR3 memory device 202h receives and acts on the received clock and command signals last after DDR3 memory devices 202a-202g. 
When a write command is provided to the DDR3 DIMM 200, each DDR3 memory device 202a-202h will see the command at a slightly different time, and as a result, will need to receive data on the data/DQS lines 206 at a slightly different time in order to align the data with the command on the DDR3 DIMM 200. Similarly, when a read command is provided to the DDR3 DIMM 200, each DDR3 memory device 202a-202h will provide the requested read data on its data/DQS lines 206 at a slightly different time. Thus, each DDR3 memory device 202a-202h receives the system clock at a slightly different time, thus requiring the DQS signal to be asserted at a slightly different time for each DDR3 memory device 202a-202h to properly align the Data strobe with the system clock at each device. Although the data clock has a fixed relationship to the data strobe at each device, the fly-by topology of the DDR3 DIMM 200 causes the each data strobe and data clock to have an asynchronous relationship with the system clock. Thus, DDR3 SDRAM presents asynchronous clock domains between the system clock and the data clock at each DDR3 memory device 202a-202h, resulting in unknown timing relationships at design.
In view of the foregoing, there is a need for systems and methods for transferring data between asynchronous clock domains. The methods should allow for synchronizing data transfer when the relationship between the asynchronous clock domains is not known at the time of the design of the system.